The present invention generally relates to semiconductors and more specifically to signal routing within integrated circuit design.
The layout for large-scale integrated microchips is one of the most time consuming tasks in the design cycle for an integrated circuit (IC). The input to this layout is a partitioned circuit, i.e., elementary components of the circuit are grouped to build a number of macro cells (modules). On the borders of these cells, signal trace endpoints or terminals are located to provide signal paths between circuit blocks of the IC and connection layers such as metal or polysilicon layers. These connection layers, also known as interconnects, require some finite width and thickness to ensure reliability of the interconnect and signal integrity.
The output of this design process is a layout for the integrated circuit. The layout describes the placement of the macro cells and the routes for the interconnects between the macro cells. One objective in layout optimization may be to find an arrangement that minimizes overall area. Cells are not allowed to overlap each other, and the routing has to meet specific technical constraints, i.e., space between parallel wires has to be added to prevent short circuits and transmission effects, and for some critical traces the delay has to stay below a given threshold, which results in maximal admissible wire lengths for these traces.
Many methods to manage a large number of associated interconnects when laying out an IC have been attempted. A common method for routing unique signals to individual macros involves a design with signal connection point(s) defined within the macro itself (hard macros). These signal connection points are manually (or via a software routing tool) creating the signal bus that connects the signal sources to the corresponding connection points. For this method, it is assumed that a routing channel is left within or above the macro during the course of the macro design.
When numerous signal paths are required between circuit blocks, the routing congestion caused by placement of the associated interconnects will increase the overall size of the IC and thus increase the cost of the product. That congestion has an increased effect when the area between the circuit blocks is limited. A further problem arises when numerous tightly spaced functional blocks require a high number of signal paths between these blocks. The associated numerous interconnects will cause even more IC area congestion that will further increase the IC size and associated cost.
The present invention overcomes the disadvantages and limitations of the prior art by providing a method and apparatus to reduce or eliminate the need to connect individual macro cell signals with traces that are supplemental to the macro cell layout. This method and apparatus to manage a large number of associated interconnects when laying out an integrated circuit involves taking a modular approach to macro cell layout. In circumstances where a macro can be employed for multiple instantiations, and where such design signals must be distributed to each instantiation, certain commonalities may exist which can be exploited to achieve a simple yet elegant approach facilitating the routing of these unique signal paths. This invention facilitates routing these unique signal paths with minimal cost and space while significantly reducing the design effort. The routing can be performed by establishing a modular xe2x80x9clibraryxe2x80x9d of macros and then physically placing these macros adjacent to one another so that the signal connections are made to the adjacent macros.
The present invention may, therefore, comprise a method of laying out internal signal paths in integrated circuit macro cells that minimizes the need for external signal paths comprising; placing a first macro cell with input and output premapped interconnect locations such that the internal signal paths that propagate through the first macro cell reach an outgoing edge of the first macro cell at standard output premapped interconnect locations; placing a second macro cell adjacent to the first macro cell such that the standard output premapped interconnect locations of the first macro cell physically align with input premapped interconnect locations of the second macro cell.
The present invention may also comprise an integrated circuit macro cell having a standard signal interconnect layout for connecting to additional macro cells comprising; a standardized configuration of input premapped interconnect locations for receiving signals from signal paths of the additional macro cells at an incoming edge of the macro cell; signal paths propagated through the macro cell that reach an outgoing edge of the macro cell at standard output premapped interconnect locations such that the output premapped interconnect locations of the macro cell physically align with the input premapped interconnect locations of the additional macro cells.
The present invention may also comprise an integrated circuit with macro cells placed adjacent to one another comprising; a first macro cell having standard input premapped interconnect locations such that the internal signal paths that propagate through the first macro cell reach an outgoing edge of the first macro cell at standard output premapped interconnect locations; a second macro cell that is placed adjacent to the first macro cell such that the standard output premapped interconnect locations of the first macro cell physically align with input premapped interconnect locations of the second macro cell.
IC designs that are capable of exploiting these types of macro layout designs are advantageous over current designs because they require less signal routing, and therefore, less design time and effort, a reduction in circuit area and overall wire trace length. In addition, other technical constraints such as short circuits, transmission effects, and signal delays can be addressed directly within the macro design.
Numerous advantages and features of the present invention will become readily apparent from the following detailed description of the invention and the embodiment thereof, from the claims and from the accompanying drawings in which details of the invention are fully and completely disclosed as a part of this specification.